1. Field of the Invention
This invention relates to a semiconductor device having fully depleted MOSFETs formed on an SOI substrate or bulk substrate to configure a CMOS circuit of high operation speed and low power consumption in a semiconductor integrated circuit device and a manufacturing method of the same.
2. Description of the Related Art
In the present system LSI, MOSFETs configuring the system LSI are miniaturized to further enhance the performance thereof. In this type of device, the reliability of the device is degraded if the power supply voltage is not lowered. At the same time, however, if the power supply voltage is lowered, the current drive is lowered. Therefore, in order to adequately maintain the current drive, it is necessary to lower the threshold voltage (Vt) with a lowering in the power supply voltage.
Generally, if the threshold voltage is lowered, an off leakage current will increase and the short channel effect caused by a reduction in the gate length also occurs. Therefore, the power consumption in the standby state of the whole chip becomes higher and this develops into a serious problem.
Thus, when the device size is miniaturized, it is necessary to maintain the cutoff characteristic of the current characteristic of the MOSFET in a good condition.
The cutoff characteristic in the Id-Vg characteristic of the MOSFET is characterized by an inclination of the Id-Vg characteristic curve of the sub threshold region and is expressed by an S value (sub threshold swing S: S-factor) as shown in the following equation (1).S=[d(log10 Id)/dVg]−1  (1)
The S value of the equation (1) indicates gate voltage required to lower the drain current value by one order. In the MOSFET using a typical bulk substrate, the S value is approximately 70 to 100 mV/dec.
It is understood that the equation (1) can be expressed by the following equation (2) based on the analytic equation of the drain current Id in the sub threshold region of the ideal MOSFET.S=(KBT/q)(loge 10)[1+Cdm/Cox]  (2)
where KB indicates Boltzmann's constant, T indicates absolute temperature, q indicates an element charge, Cdm (=sqrt(εsiqNa/4 φB) indicates depletion capacitance in the substrate and Cox indicates capacitance of the gate oxide film, respectively.
It is known that the depletion layer particularly on the drain region side extends when the gate length is miniaturized, the potential in a portion near the channel of the MOSFET is deviated from the ideal potential (DIBL: Drain Induced Barrier Lowering) and the S value becomes larger.
That is, it is desirable at present and in future to realize a device structure in which the S value can be kept small even if the gate length is reduced.
Further, if the S value is kept small, the roll-off of the threshold voltage Vt (=the relation between Vt and the gate length) in the so-called short-channel effect is suppressed, which is favorable.
An FD (Fully Depleted) type MOSFET, whose channel region is fully depleted, is conventionally proposed as the MOSFET structure having a small value of Cdm. As a variation of the FD type MOSFET, various types of MOSFETs, such as a planar type single gate SOI structure (FD-SOIMOSFET), planar type double gate structure, fin type double gate structure (refer to a Patent Document 1, Non-Patent Documents 1, 2), vertical structure (refer to Non-Patent Document 3) and tri-gate structure (refer to Non-Patent Document 4) are already provided.
The FD type MOSFETs have both merits and demerits, but it intuitively seems that the double gate structure (planar type, fin type) and tri-gate structure are advantageous by taking it into consideration that the cutoff characteristic is better than the conventional single gate structure.
However, in the planar type among the double gate structure, it is difficult to arrange gate electrodes in the upper and lower positions in a self-aligned manner and there occurs a problem that the manufacturing method becomes complicated. On the other hand, in the fin type among the double gate structure, it is relatively easy to form the double gate structure, but there occurs a problem that the fin width must be made extremely small. Further, since a substrate is cut out in a fin form by use of an RIE (Reactive Ion Etching) process and the side surface portion thereof is used as a channel, it is difficult to use the substrate surface having a plane orientation of <100> used in the planar type. In this case, there occurs a possibility that the interface state density becomes high, thus a problem that the reliability may be lowered occurs.
Further, as shown in FIG. 62, the tri-gate structure is a device in which both of the side surface and upper surface of an SOI layer 113 are used as a channel in an SOI substrate having a supporting substrate 111, buried oxide film (BOX: Buried Oxide) 112 and SOI (Silicon On Insulator) layer 113. The source and drain regions lie on the front side and opposite side of the drawing sheet. The device is controlled by use of gate electric fields in three directions to suppress the punch through between the source and drain regions and enhance the current driving ability. However, like the fin type double gate structure, the tri-gate structure has a problem that the characteristic of a transistor formed on the side surface may not be good. Further, since an electric field caused by a gate electrode 114 is concentrated on corner portions 115 between the upper surface and the side surfaces, parasitic transistors having low threshold voltages are formed only in the corner portions 115. As a result, there occurs a possibility that the cutoff characteristic of the transistor on the channel upper surface portion used as a main transistor will be degraded due to a difference between the characteristic of the transistor on the corner portion 115 and the current characteristic of the transistor on the channel upper surface portion.
[Patent Document 1]
Jpn. Pat. Appln. KOKAI Publication No. 2-263473 (Patent Registration No. 2768719)
[Non-Patent Document 1]
D. Hisamoto et al., “International Electron Devices Meeting (IEDM) '98”, p. 1032
[Non-Patent Document 2]
X. Huang et al., “IEDM '99”, 1999, p. 67
[Non-Patent Document 3]
J. Hergenrother et al., “IEDM '99”, 1999, p. 75
[Non-Patent Document 4]
R. Chau et al., “International Conference of Solid State Devices and Materials (SSDM) 2002”, 2002, p. 68
As described above, in the conventional various FD type MOSFETs, it is difficult to attain a favorable cutoff characteristic without making thin a silicon layer used as a channel in a region in which the channel length is short.